1. Field of the Invention
This invention is related to the field of interconnects for electronic systems such as computer systems.
2. Description of the Related Art
Electronic components in systems (such as integrated circuits and other electrical devices) communicate with each other over defined interfaces such as links between the components. Data is usually transmitted over the links with reference to a clock signal. That is, data is driven and sampled on the link responsive to the clock signal. Recently, double data rate links have been defined in which data is driven/sampled according to both the rising and falling edges of the clock signal.
The frequency of the clock associated with a link, along with its width (in bits of data transferred) defines the bandwidth on the link (the amount of data transferred per unit time). One way to increase bandwidth (and also decrease latency, for larger transfers) is to increase the clock frequency. However, as the frequency increases, the error rate also increases as factors such as noise, clock uncertainty, skew, rise and fall times, etc. become bigger factors in the shorter clock cycle. Viewed in another way, data is present on the link for a shorter period of time, and the margin for error is smaller. At some point, the error rate increases to a level that impacts reliability.
To mitigate the increased error rate, error detection (and possibly correction) can be implemented on the link. For example, a cyclical redundancy check (CRC) is often implemented on links. For CRC, each data transfer on the link is followed by a CRC code that is generated from the data. The receiver can generate the same CRC code, and compare the generated CRC code to the received code to detect an error. The receiver can report the error to the transmitter, which can retransmit the data or take other corrective action.
For relatively large data transfers, the addition of the CRC code to the end of the transfer doesn't impact bandwidth very much (since the added code is small compared to the data transferred). However, the CRC code does impact latency, as the receiver generally must store the entire data covered by the CRC until the CRC is received. If the CRC validates that the data is correct, then the data can be forwarded. In many cases, the first data in the transfer is the most critical (e.g. in caching systems in which the data that is currently requested is transferred first, followed by the remainder of the cache block for storage). In such cases, the increase in latency is a decrease in performance.
Furthermore, in coherent systems, many of the transfers between components are relatively small messages (e.g. probes searching for the most recent copies of the data, probe responses, done indications for source and target, etc.). The impact of the CRC on these small messages is significant, increasing the size of the messages by as much as 100% (for a message that is the same size as the CRC code). Size increases of 50% or 33% are common as well. In coherent systems, a large number of the transfers over the links are these small messages, so the increased bandwidth consumed to add the CRC is significant.